In semiconductor technology that processes a backside of a wafer, such as a backside illuminated complementary metal-oxide-semiconductor imaging sensor (CIS) or charge-coupled device (CCD), a carrier substrate typically needs to be bonded to the front side of the wafer. The carrier substrate thereby sandwiches circuitry such as multilayer interconnects between it and the wafer substrate (the imaging sensor wafer). This allows the backside silicon of the imaging sensor wafer to be processed, such as in a chemical-mechanical polish (CMP).
Traditional bonding pads are formed near a top surface of the imaging sensor wafer for use in wafer level test and wire bonding during chip packing. However, when the traditional bonding pad structure is applied to the backside illuminated image sensor application, the formed bonding pads are located between the carrier substrate and the imaging sensor wafer and are difficult to access. Also, additional patterning and etching steps may need to be applied to various silicon layers and interconnection layers before wafer packaging, resulting in higher manufacturing and testing cost and other quality issues.
Therefore, the application and use of bonding pads, such as in a backside illuminated sensor, is desired.